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| order this document by AN1816/d ? motorola, inc., 1999 AN1816 AN1816 using the hc912b32 to implement the distributed systems interface (dsi) protocol by tracy mchenry august 1999 introduction system design requirements are continually changing as systems become increasingly complex. in conventional systems where sensors and actuators are connected directly to a microcontroller (mcu), the number of pins available on the mcu limits system expansion. as a result, extra costs can be incurred if another mcu is required or if the hardware has to be redesigned to accommodate a higher pin count mcu. an alternative approach is to move to a distributed bus architecture. this option allows one master mcu to interconnect to many remote sensors and actuators. the distributed systems interface (dsi) is one such master/slave system, with the central control module being the master and the remote sensors and actuators acting as slave devices. a key feature of the dsi architecture is that the sensors and actuators can be connected on the same bus. another benefit of the dsi is that it promotes the use of standard components and interfaces which enables maximum re-use and accelerates time to market. this is a great advantage to systems designers who are therefore able to develop flexible system solutions. it was initially developed for the automotive market although it is equally suited to other applications that require distributed sensors and/or actuators. examples of possible dsi applications include occupant safety systems, body networks, building and industrial controls. this application note provides an overview of the dsi and describes the hardware and software design of a demonstrator system. f r e e s c a l e s e m i c o n d u c t o r , i f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
AN1816 2 application note distributed systems interface (dsi) overview the distributed systems interface (dsi) was designed to interconnect multiple remote sensor and actuator devices to a central control module. it provides simultaneous support for sensors and actuators using a 2-wire bus that provides both power and communications. this results in savings in wiring costs and connector complexity. unlike conventional systems, the size of the connector for the control module does not need to grow to accommodate every new sensor or actuator. a new sensor or actuator can be added to the bus without reconfiguring the system design. the dsi, therefore, enables the development of easily expandible systems. the dsi communication bus is simple yet robust. signals are superimposed onto the power line and, as communication between the master and slave nodes is bi-directional, the dsi makes efficient use of bus bandwidth. also, to ensure message integrity, each message contains a 4-bit cyclic redundancy check (crc). slave nodes can be attached to the bus in daisy chain or parallel connections. each slave device on a bus has a unique address. the daisy chain connection allows the central module to establish the node addresses at power-up. the parallel configuration can be used for devices that have pre-programmed or fixed addresses. it is possible to have a combination of the two on one bus with the maximum number of nodes on a dsi bus being 16 (1 master and 15 slaves). signalling the dsi uses two mediums for signalling - voltage mode for messages from the master to the slaves, and current mode for the responses from the slaves. voltage mode encoding the voltage mode signal bits are sent on a 2:1 ratio as shown in figure 1 voltage mode bit encoding . figure 1 voltage mode bit encoding logic 1 logic 0 logic 0 logic 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 3 distributed systems interface (dsi) overview the dsi protocol has been designed such that the first third of a voltage mode signal bit is always low and the last third is always high. the central third defines the signal value. for a logic zero the master produces a signal that is low for 2/3 of the bit time and high for the final 1/3. for a logic one the signal is low for 1/3 of the bit time and high for 2/3 of the bit time. each slave has a built-in oscillator. this feature of the dsi message protocol has created a high immunity to temporal distortion. consequently, each slave ic is simpler and cheaper to design while still able to capture all messages accurately. an added benefit is that it allows for a range of operating frequencies. bus voltage levels the voltage mode signalling uses a tri-level bus as shown in figure 2 tri-level bus . figure 2 tri-level bus the dsi bus provides power to the slave nodes as well as supporting bi-directional communication between the slave nodes and the master. when the bus is at the idle voltage, which ranges from 8 to 25 volts, it supplies power to the slave nodes. a high threshold level (typically 6v) and a low threshold level (typically 3v) play a significant part in message transmission. the start of a word occurs when the bus voltage drops from the idle voltage below the high threshold level and then below the low threshold level. data values are determined by the ratio of time spent above and below the low threshold. the voltage rising above the high threshold level signals the end of a word. current mode encoding slave responses to commands are returned by modulating the amount of current sunk by the device. this is measured at the end of each bit to determine a zero or one response. when responding with a logic one, idle high threshold signal high low threshold signal low gnd end of first bit ("0") end of word start of word end of second bit ("1") start of next word f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 4 application note the slave draws additional current from the source during the bit time. conversely, no extra current is drawn when responding with a logic zero. figure 3 current waveform shows a representation of the current waveform referenced to a voltage waveform. figure 3 current waveform message format dsi messages are composed of individual words separated by a minimum frame delay. transfers are full duplex, that is, command messages from the master occur at the same time as responses from the slaves. this is an important feature of the dsi as it doubles the effective signal bandwidth. slave responses to commands occur during the next command message. this allows slaves time to decode the command, act upon it and then respond to the master. the minimum frame delay is present to allow recharge of energy storage devices in the slaves. this is necessary because the slave receives its power from the signal line. message encoding message encoding depends on the direction of the transfer. command and control messages are sent from the master to the slave. response messages are sent from the slaves to the master. in both cases there are long word and short word messages. a long word consists of 16-bits of information followed by a 4-bit cyclic redundancy check (crc). a short word is composed of 8-bits of information followed by the 4-bit crc. voltage (from master) current (from slave) logic 1 logic 0 logic 0 logic 1 logic 1 logic 0 logic 1 logic 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 5 distributed systems interface (dsi) overview command and control messages the long word command and control message encoding is shown in figure 4 long word command and control message . the message consists of 8 bits of data, the encoded 4-bit address of the intended slave device, a 4-bit encoded command, and the calculated 4-bit crc. the short word command and control message encoding is shown in figure 5 short word command and control message . the message consists of the encoded 4-bit address of the intended slave device, a 4-bit encoded command, and the calculated 4-bit crc. response messages a long word response message is sent from the slave to the master in response to a long word command and control message to the slaves address. the response is transmitted during the next command and control message. the long word response message encoding is shown in figure 6 long word response message . the message consists of two 8-bit data bytes and the calculated 4-bit crc a short word response message is sent from the slave to the master in response to a short word command and control message to the slaves address. the response is transmitted during the next command and data address command crc d7 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 c3 c2 c1 c0 x3 x2 x1 x0 figure 4 long word command and control message address command crc a3 a2 a1 a0 c3 c2 c1 c0 x3 x2 x1 x0 figure 5 short word command and control message data byte 1 data byte 2 crc d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x3 x2 x1 x0 figure 6 long word response message f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 6 application note control message. the short word response message encoding is shown in figure 7 short word response message . the message consists of one 8-bit data byte and the calculated 4-bit crc. long words are always sent in response to long word commands and short words are always sent in response to short word commands. when the word format changes between successive commands, the first response sent during the new format will be invalid since it will not have the proper number of bits. error checking the master and slaves calculate a crc on the information portion of their received messages. the message is valid only if the calculated crc matches the crc sent as part of the message. an error bit is set in the master when it receives an invalid message. the slaves discard and ignore all invalid received messages and in addition do not respond to them. slave device addressing each slave device on the bus must be given a unique 4-bit address (from 1 (0001) to 15 (1111)) and assigned to one of four groups. address 0 (0000) is used to address all 15 slave nodes at once. programmable devices after system power up the master must set the address of all daisy chain slave devices with programmable addresses before network communications can commence. these devices have a bus switch on the power/signal line. at power up the programmable device bus switches are open and only close once an initialisation message has been received. with the first bus switch open, the bus only goes as far as the first slave. when the master sends a slave initialisation command, the first slave device stores its address information and closes its bus switch. the second daisy chain slave is now connected to the network. when the master initialises the second slaves address, the first device responds with an initialisation response message. the response message echoes the programming information back to the master so that it knows that the address was successfully established. each slave sends the initialisation response message only once after receiving a program address command message. data c r c d7 d6 d5 d4 d3 d2 d1 d0 x3 x2 x1 x0 figure 7 short word response message f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 7 hardware design an advantage of having programmable devices present in the system is that they may be replaced and/or the system may be reconfigured by adding nodes to the bus and the system will automatically reconfigure itself at the next power up. pre-programmed devices slaves with pre-programmed addresses do not require a bus switch. on power-up the stored pre-programmed address becomes the slave address. however, pre-programmed devices must still receive an initialisation command and reply with an initialisation response before responding to any other bus commands. hardware design figure 8 top level dsi system connections several ics are used in the development of the system : ? master board C hc912b32 C mc68hc55 spi peripheral C mc33790 bus transceiver ? slave board C evaluation slave device, the bem ic dsi0o dsi1o gnd gnd mc33790 bus transceiver clk di do cs* sclk ch.0 ch.1 mc68hc55 spi peripheral pwm pin sck mosi miso i/o pin spi (master ) hc912b32 mcu dsi0f dsi0s dsi0r dsi1f dsi1s dsi1r two-wire bus signal return g n d b u s i n b u s o u t slav master board f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 8 application note master board figure 8 top level dsi system connections shows how the ics are connected together. it should be noted that the diagram shows a daisy chain connected slave but slave nodes can also be connected onto the bus in parallel. the parallel configuration is used for slave nodes that have pre-programmed addresses. the spi of the hc912b32 is set up such that it acts as the master and all communication from the hc912b32 to the mc68hc55 is via the spi. the mc33790, the physical layer interface to the dsi bus, sends commands to and receives responses from the slave devices. software required to control the system can be programmed into the hc912b32s 32k of flash memory. it also has 768 bytes of eeprom and 1k of ram. the pwm is used to provide the mc68hc55 with a system clock. it is set up such that pwm channel 0 is output on port p pin 0 (pp0) and connected to the sclk pin of the mc68hc55 spi peripheral. the hc912b32s on board spi is a key element in the dsi communication protocol and is set up as follows. the mosi, miso and sclk pins on the hc912b32 are connected to the mc68hc55s di, do, clk pins respectively. port s pin 7 (ps7) is connected to the cs pin on the mc68hc55. it should then be defined in the software as a general-purpose i/o pin and set up to drive cs on the mc68hc55. cs is an active low signal that is controlled by the hc912b32. when driven low it indicates the start of message transmission from the hc912b32 to the mc68hc55 and in turn to the mc33790 and then to the slave nodes. this is the start of what is termed a spi burst transfer (refer to the sub section: initialisation of the pwm and spi in the software design section of this application note). the end of a spi burst transfer is signalled by the hc912b32 pulling cs high. commands are sent to and responses are received from the slave nodes via the spi during a burst transfer. the data written to the spi data register is transferred into the mc68hc55s data register, which transmits the message to the slave nodes via the mc33790 bus transceiver. the mc68hc55 is the protocol controller of the system and controls all the digital functions of the dsi. it contains 2 independent dsi channels, each capable of interfacing to up to 15 slave nodes. the mc68hc55 spi peripheral uses 3 pins to transmit a message to the mc33790 bus transceiver. pin dsixs (signal) on the mc68hc55 transmits the data output signal to the mc33790. data bits on this signal line are pulse length encoded voltage levels. a logic zero starts with a falling edge on dsixs and is low for two thirds of the bit time and then high for one third of the bit time. a logic one starts with a falling edge on dsixs and is low for one third of the bit time and then high for two thirds of the bit time. dsixf (frame) output pin idles high and is driven low during each transfer frame. dsixr is the data input signal from the mc33790. the mc68hc55 samples the cmos level on this pin at the end of a bit time. this level corresponds to the current sensed by the mc33790. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 9 hardware design the mc33790 bus transceiver is an analogue smartmos? device, which serves as the physical interface to the two-wire dsi bus. it uses a combination of pulse length encoded voltage levels for transmit data to slave nodes and current return signals for receive data at the same time. figure 9 mc68hc55 frame and output signals with respect to mc33790 dsix0 signal when the mc33790 receives data for transmission to the slave nodes from the mc68hc55, its bus transmitter circuit converts the 0 to 5 volt inputs from the mc68hc55s dsixf (frame) and dsixs (signal) to a voltage level on the output dsixo which connects to bus_in of the first slave node. the value output on dsixo of the mc33790 depends on the values of dsixf and dsixs as shown in table 1 dsixo truth table . see also figure 9 mc68hc55 frame and output signals with respect to mc33790 dsix0 signal . when the mc33790 is receiving data from the slave nodes, it samples the current responses on the rising edge of the final third of bit time. the current response is then compared against a reference point, which determines whether a low or high has been returned. dsixf (frame) from mc68hc55 dsixs (signal) from mc68hc55 dsixo from mc33790 idle idle high low dsixf dsixs dsixr dsixo 0 0 return data low (1.5v) 0 1 return data high (4.5v) 1 0 0 high impedance 1 1 0 idle table 1 dsixo truth table f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 10 application note schematics and layout considerations - master board figure 10 master board schematic figure 10 master board schematic shows the schematic for the master board. the board was based on an existing hc912b32 evaluation board (evb) with the addition of the required dsi circuitry. the hc912b32 evb circuitry allows the board to be used to evaluate prototype hardware and software. when laying out the dsi circuitry on the master board, the bus traces out of the mc33790 were made as wide as possible to deal with the presence of the higher voltage (the dsi bus maximum idle voltage is 25v). all components were positioned where clock and bus trace lengths could be kept to a minimum. 0.1 m f capacitors were used to filter the bus supply voltage and to decouple the power supplies to the mc68hc55 and mc33790. these capacitors were placed as close to the ics as possible. sclk clk di do cs reset int gnd vdd dsi0f dsi0s dsi0r n.c. dsi1f dsi1s dsi1r dsi0f dsi0s dsi0r dsi1f dsi1s dsi1r n.c. cpcap vdd gnd0 dsi0o vsup dsi1o gnd1 n.c. n.c. c22 0.1 m f 116 215 314 413 512 611 710 89 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 u9 - dsid u11 - dsip w19 - tp2 dsi ch.1 rx data dsi ch.0 rx data w17 - tp1 c23 0.1 m f vdd c24 0.1 m f vdd w18 r15 100 w pp0/pw0 ps6/sck ps5/mosi ps4/miso ps7/ss ps3 pe1/irq 1 1 c26 10 m f + w21 n.c. no pin 25v gnd bus power w20 w22 dsi0 dsi1 mcu pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 11 hardware design slave board the slave board discussed in this application note is one that was designed as part of a dsi evaluation tool kit. it contains the bus evaluation module (bem) ic, which is a slave dsi interface evaluation device. it provides bi-directional communications from the dsi bus. the slave board contains an on board potentiometer which can be used to vary the voltage input to the bem ic. this voltage is converted by the bem ic to a digital signal that is then transmitted over the dsi bus. alternatively, an accelerometer or other analogue output device could be connected using the wire wrap area of the slave board and the jumper setting changed such that the output of the accelerometer is input to the bem ic. multiple slave nodes can be attached to one dsi bus by daisy chaining them together. schematics and layout considerations - slave board figure 11 slave board schematic date: august 10, 1999 sheet 1 of 1 size document number rev b slave.sch title slave board occupant safety systems date description rev r e v i s i o n s slave board bus signals from ecu gnd vr1 1 2 3 j1 d1 diode zn1 gnd bus_in 1 gnd 2 bus_out 3 u3 con3way vreg busout busin sigin tp1 test point tp2 test point tp3 test point tp4 test point c2 4.7uf bus_out 16 vreg 10 n/c 9 n/c 8 bus_in 14 bus_gnd 1 bus_gnd 12 agnd 5 agnd 6 2 4 sig_in 7 filt_cap 11 n/c 3 n/c 15 n/c 13 u4 bem ic d2 diode zn1 1 2 r2 10k gnd 1 2 r1 10k gnd 1 2 c3 0.1uf gnd gnd c1 1.0uf gnd computer generated drawing : do not revise manually f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 12 application note figure 11 slave board schematic shows the schematic for the slave board. a benefit of the dsi architecture is that the slave board requires only a few additional components. zener diodes are used to protect against esd damage to signals busin and busout. c1 (filt_cap) supplies the power to the bem ic during signalling. when laying out the slave board, the pads for capacitor, c1 were enlarged so that they could accommodate various values of capacitor from 1 m f up to 4.7 m f depending on what was required of the evaluation system. for the slave node described in this application note a 1 m f capacitor was selected as being capable of storing enough charge to power the bem ic during signalling. all components were positioned where signal trace lengths could be kept to a minimum and signal traces were made as wide as possible. also, analogue and digital grounds were connected together as close to the bem ic as possible. software design the initialisation software can be divided into 3 sections - initialisation of the pwm and spi, initialisation of the mc68hc55 spi peripherals registers and initialisation of the slave nodes. initialisation of the pwm and spi the pwm on the hc912b32 provides the system clock (sclk) for the mc68hc55 spi peripheral. the system software must initialise the pwm so that it supplies a clock signal to the mc68hc55 spi peripheral with the appropriate duty cycle and period. an example of possible c source code that can be used to perform this set-up is shown in function initpwm in appendix 1 - source code . the pwm registers, in this example, are set up to generate a clock signal with a duty cycle of 50% and a period of 3.5 m s (frequency of 285khz). the spi is set up such that the slave select (ss ) pin on the hc912b32 (connected to chip select (cs ) on the mc68hc55 spi peripheral) is configured as a general purpose i/o pin allowing the software to control it. this is necessary for spi burst transfers, thus enabling the hc912b32 to communicate with the slave nodes via the mc68hc55 and the mc33790. figure 12 spi burst transfer example shows an example of an spi burst transfer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 13 software design figure 12 spi burst transfer example when cs is driven low by the hc912b32, the mc68hc55 spi peripheral is enabled and the first spi transfer after this is a command transfer. bit7 of this command determines if it is a read (0) or a write (1) command. bits[2:0] specify the address of one of the eight mc68hc55 registers and an internal pointer is established. data sent back to the hc912b32 from the mc68hc55 during a command transfer is read data from the adress previously pointed to (this would be all zeros for the first transfer after reset). any additional transfers result in a write-to or read-from successive registers in the mc68hc55. the internal register pointer is incremented at the end of the transfer and will roll over from 7 (111) to 0(000). cs remains low throughout the whole burst sequence and is driven high at the end by the hc912b32. possible software routines to perform the spi set-up and to control the transfer of data in spi burst mode are shown in the source code detailed in functions initspi and spiburst in appendix 1 - source code . initialisation of the mc68hc55 spi peripheral? registers table 2 dsi registers shows the mc68hc55 registers. the hc912b32 can read-from or write-to the mc68hc55s seven registers through the spi interface. data to be transferred to the slave nodes is written into the clk di do cs* command C wrt (000) write dsi0l (001) write dsi0h (000) zeros (1 st transfer after reset) read dsi0l (001) read dsi0h (000) dsi0h - data access for dsi/d channel 0 (high byte) address - 000 bit 7 6 5 4 3 2 1 bit 0 bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 high dsi0l - data access for dsi/d channel 0 (low byte) address - 001 bit 7 6 5 4 3 2 1 bit 0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 low table 2 dsi registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 14 application note dsixh:dsixl register pair for 16-bit messages; dsixl for 8-bit. the transfer begins once dsixl has been written to. similarly, responses from the slave nodes are written into these registers. the dsistat register provides status information and should be checked before and after transfers. it contains an error flag, erx, which indicates if the master received an invalid crc value. also, transmit and receive status information, tfex, tfnfx and rfnex, is available through this register. the dsixctrl register is written to before data is sent over the dsi bus. this register is used to specify an additional divider between the sclk input and the bit timing circuitry, cdivx[b:a], as well as defining the dsi1h - data access for dsi/d channel 1(high byte) address - 010 bit 7 6 5 4 3 2 1 bit 0 bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 high dsi1l - data access for dsi/d channel 1(low byte) address - 011 bit 7 6 5 4 3 2 1 bit 0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 low dsistat - dsi status register address - 100 bit 7 6 5 4 3 2 1 bit 0 er1 tfe1 tfnf1 rfne1 er0 tfe0 tfnf0 rfne0 dsi0ctrl - dsi channel 0 control register address - 101 bit 7 6 5 4 3 2 1 bit 0 cdiv0b cdiv0a dly0b dly0a rie0 tie0 0 ms0 dsi1ctrl - dsi channel 1 control register address - 110 bit 7 6 5 4 3 2 1 bit 0 cdiv1b cdiv1a dly1b dly1a rie1 tie1 0 ms1 dsienabl address - 111 bit 7 6 5 4 3 2 1 bit 0 0 0 0 0 0 0 en1 en0 table 2 dsi registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 15 summary interframe delay, dlyx[b:a]. it is also used to enable interrupts, riex and tiex, and to select 12 -bit (8 data bits plus 4 crc bits) or 20-bit (16 data bits plus 4 crc bits) messages, msx. this register is updated as soon as new data is received over the spi interface, however, the new value does not take affect until the next dsi clock cycle after the conclusion of the spi write to this register. finally, the dsienabl register is used to enable or disable each dsi channel. the function setupdsi shown in the source code in appendix 1 - source code is an example of how to set up the mc68hc55 spi peripherals registers. it uses the spi burst routine discussed in sub section: initialisation of the pwm and spi and sets up the registers for initialisation of the programmable slave nodes. initialising the slave nodes programmable devices the source code shown in the main section of the program that calls functions pgmaddr, pgmchk and chkrsp in appendix 1 - source code details a very simple routine to program the addresses into slave nodes. it programs 15 slave nodes sequentially starting with address 1 (0001) and finishing with address 15 (1111). to ensure the response from the slave node whose address is being set is captured, the mc68hc55s clock period is set to sclk divided by 4 and the interframe delay is set to 32 bit times. this is achieved by writing $b0 to the mc68hc55s dsixctrl register (refer to sub section: initialisation of the mc68hc55 spi peripherals registers ). pre-programmed devices when the network is configured with pre-programmed devices the initialisation procedure is similar to that of programmable devices. an initialisation command that contains the address of the slave node being initialised is sent to that slave node. the slave node then responds to the initialisation command to let the master know it is present in the network. summary this application note has discussed a total system solution using a full suite of freescale ics. although the initial target application is automotive airbag systems it could be used in other applications which require remote sensors. the distributed systems interface (dsi) has many advantages in that it allows flexibility of system design, is easily expandible and allows the central module size to decrease while the system content grows. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 16 application note references 1. dsi specification; internal freescale document 2. mc68hc55 spi peripheral specification; data sheet, order number mc68hc55/d 3. bem specification; only available with dsi evaluation system (contact sales office for more details) 4. mc33790 physical layer asic specification; internal freescale document 5. mc68hc912b32 advance information; order number mc68hc912b32/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 17 appendix 1 - source code appendix 1 - source code /********************************************************************************** file : b32dsi.h header file referenced in program initb32dsi.c to define the register addresses of the cop, pwm and spi ***********************************************************************************/ /* define cop register */ #define copbase (volatile char *const)(0x16) #define copctl (*(copbase+0)) /* define porta for general purpose i/o */ #define ptabase (volatile char *const) (0x00) #define porta (*(ptabase+0)) #define ddra (*(ptabase+2)) /* define pwm registers */ #define pwmbase (volatile char *const)(0x40) #define pwclk (*(pwmbase+0)) #define pwpol (*(pwmbase+1)) #define pwen (*(pwmbase+2)) #define pwres (*(pwmbase+3)) #define pwper0 (*(pwmbase+0xc)) #define pwdty0 (*(pwmbase+0x10)) #define pwctl (*(pwmbase+0x14)) #define portpp (*(pwmbase+0x16)) #define ddrp (*(pwmbase+0x17)) /* define spi registers */ #define spibase (volatile char *const)(0xd0) #define sp0cr1 (*(spibase+0)) #define sp0cr2 (*(spibase+1)) #define sp0br (*(spibase+2)) #define sp0sr (*(spibase+3)) #define sp0dr (*(spibase+5)) #define ports (*(spibase+6)) #define ddrs (*(spibase+7)) #define purds (*(spibase+0xb)) /********************************************************************************** file : initb32dsi.c c code to be programmed into the flash of the hc912b32 which initialises the pwm and spi of the hc912b32 then sets up the dsi registers on the mc68hc55 spi peripheral i.c. before programming the address into 15 programmable slave nodes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 18 application note this source code is example code that could be used to perform initialisation. freescale reserves the right to make changes without further notice to any product herein to improve reliability, function, or design. freescale does not assume any liability arising out of the application or use of any product, circuit or software described herein; neither does it convey any licensed under its patent rights nor the right of others. freescale products are not designed, intended or authorised for use as components intended for surgical implant into the body, or other applications intended to support life, or any other application in which failure of the freescale product could create a situation where personal injury or death may occur. should buyer purchase or use freescale products for any such intended or unauthorised application, buyer shall indemnify and hold freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorised use, even if such a claim alleges that freescale was negligent regarding the design or manufacture of the part. freescale and the freescale logo are registered trademarks of freescale semiconductor, inc. ***********************************************************************************/ #include AN1816 19 appendix 1 - source code sp0cr1 = 0x10; /* enable master mode and ssoe=0, therefore ss is gp i/o */ sp0cr1 = 0x50; /* enable spi system now */ } /* this function is called by the spiburst function. it writes information into the spi data register and when the spi transfer complete flag is set it sends back the information received by the spi */ short transmitreceive(short sendbyte) { int dummy=0; short result; sp0dr = sendbyte; while ((sp0sr & 0x80) == 0) /* wait until spi transfer complete flag is set */ { dummy++; } result = sp0dr; return (result); } /* this function sets up the spi burst transfer routine. it enables the mc68hc55 spi peripheral by driving cs low and then transfers the required no. of bytes of data to complete the burst transfer. it finishes by driving cs high and disabling the mc68hc55 spi peripheral */ void spiburst(int bytecount) { int count; /* cs to go low */ ports = 0x00; /* transmit bytes */ for (count=0; count AN1816 21 appendix 1 - source code spiburst(2); while ((rbytes[1] & 0x01) == 0) { spiburst(2); } } /* this function programs the address into the first slave node (no response is expected ) */ void pgmaddr(int addr) { tfflag(addr); /* check tfnf0 flag is set */ tbytes[0] = 0x80; /* send 80 (write cmd to dsi0h) receive 00 */ tbytes[1] = addr; /* pgm addr cmd into dsi0h then tbytes[2] is dsi0l */ tbytes[2] = 0x00; spiburst(3); rfflag(); } /* this function programs the addresses into slave nodes 2 through to 15 and checks the responses from slave nodes 1 to 14 */ void pgmchk(int addr, int lastaddr) { unsigned short dsidat; unsigned short dsichk; int dummy=0; tfflag(addr); /* check tfnf0 flag is set */ tbytes[0] = 0x80; /* send 80 (write cmd to dsi0h) */ tbytes[1] = addr; /* pgm addr cmd written into dsi0h & dsi0l */ tbytes[2] = 0x00; spiburst(3); rfflag(); /* crc check */ if (rbytes[1] & 0x08) { flagerror(4,lastaddr); for (;;); /* error - loop until device is reset */ } tbytes[0] = 0x00; /* read dsi0h and dsi0l */ spiburst(3); dsidat = rbytes[1] | 0x0000; /* now shift dsidat 8 times */ dsidat <<= 8; dsidat = dsidat+rbytes[2]; /* now need to check the response ie that bits[15:12] = prev. slave addr */ dsidat >>= 12; dsichk = lastaddr | 0x0000; if (dsidat != dsichk) { f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 22 application note flagerror(6,lastaddr); for (;;); /* error - loop until device is reset */ } /* this function checks the response to the program address command of the last slave node (number 15) */ void chkrsp(int addr, int adccmd)) { unsigned short dsidat; unsigned short dsichk; int dummy=0; tfflag(addr); /* check tfnf0 flag is set */ tbytes[0] = 0x80; /* send 80 (write cmd to dsi0h) */ tbytes[1] = 0x00; /* cmd written into dsi0h & dsi0l */ tbytes[2] = 0xadccmd; /*dummy command to allow response from final pgm addr cmd to be captured */ spiburst(3); rfflag(); /* crc check */ if (rbytes[1] & 0x08) { flagerror(4, addr); for (;;); /*error - loop until device is reset */ } tbytes[0] = 0x00; /* read dsi0h and dsi0l */ spiburst(3); dsidat = rbytes[1] | 0x0000; /* now shift dsidat 8 times */ dsidat <<= 8; dsidat = dsidat+rbytes[2]; /* now need to check the response ie that bits[15:12] = slave addr */ dsidat >>= 12; dsichk = addr | 0x0000; if (dsidat != dsichk) { flagerror(6,addr); for (;;); /* error - loop until device is reset */ } int main (int argc, char* argv[] ) { int result=-1; short slavenum; /* the address of the slave node to be programmed */ short prevaddr; /* the address of the previous slave node whose response requires to be checked */ copctl = 0x00; /* disable cop resets */ initpwm(); /* set up pwm */ initspi(); /* set up spi */ result = setupdsi(); /* set up dsi ctrl and enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN1816 23 appendix 1 - source code registers (result=0) if all ok*/ if (result != 0) { flagerror(1,1); /* need to stop program as well */ for (;;); /* error - loop until device is reset */ } /* program the address into each slave node and check response */ /* for this version no. of slave nodes is 15 (the maximum) */ pgmaddr(0x01); for (slavenum=0x02, prevaddr=0x01; slavenum<0x10; slavenum++, prevaddr++) { pgmchk(slavenum, prevaddr); } chkrsp(0x0f, 0x02); return; } f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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